1 standard products UT54ACS373/ut54acts373 octal transparent latches with three-state outputs datasheet november 2010 www.aeroflex.com/logic features ? 8 latches in a single package ? three-state bus-driving true outputs ? full parallel access for loading ? 1.2 cmos - latchup immune ? high speed ? low power consumption ? single 5 volt supply ? available qml q or v processes ? flexible package - 20-pin dip - 20-lead flatpack ? UT54ACS373 - smd 5962-96588 ? ut54acts373 - smd 5962-96589 description the UT54ACS373 and the ut54acts373 are 8-bit latches with three-state outputs designed for driving highly capacitive or relatively low-impedance load s. the device is suitable for buffer registers, i/o ports, and bidirectional bus drivers. the eight latches are transparent d latches. while the enable (c) is high the q outputs will follow the data (d) inputs. when the enable is taken low, the q outputs will be latched at the levels that were set up at the d inputs. an output-control input (oc ) places the eight outputs in either a normal logic state (high or low logic levels) or a high-imped- ance state. the high-impedance third state and increased drive provide the capability to drive th e bus line in a bus-organized system without need for inte rface or pull-up components. the output control oc does not affect the in ternal operations of the latches. old data can be retained or new data can be entered while the outputs are off. the devices are characterized over full military temperature range of -55 c to +125 c. function table note: 1. data may be latched internally. pinouts 20-pin dip top view 20-lead flatpack top view logic symbol inputs output oc c nd nq l h h h l h l l l l x nq 0 h x x z 1 1 2 3 4 5 7 6 20 19 18 17 16 14 15 oc 1q 1d 2d 2q 3q 3d v dd 8q 8d 7d 7q 6d 8 13 4d 5d 6q 9 12 4q 5q 10 11 v ss c 1 2 3 4 5 7 6 20 19 18 17 16 14 15 oc 1q 1d 2d 2q 3q 3d v dd 8q 8d 7d 7q 6d 813 4d 5d 6q 912 4q 5q 10 11 v ss c (1) oc en (3) 1d (4) 2d (7) (2) 1q (6) (5) 2q note: 1. logic symbol in accordance with ansi/ieee std 91-1984 and iec publication 617-12. 3d (8) 4d (13) 5d (14) 6d 3q (15) 6q (12) 5q (9) 4q (17) 7d (18) 8d (19) 8q (16) 7q (11) c c1 1d
2 logic diagram oc c 1d 2d 3d 4d 5d 6d 7d 8d (1) (11) (4) (7) (8) (13) (14) (17) (18) (2) (5) (6) (9) (12) (15) (16) (19) 1q 2q 3q 4q 5q 6q 7q 8q c d c d c d c d c d c d (3) d c c d q q q q q q q q
3 operational environment 1 notes: 1. logic will not latchup during radiation ex posure within the limits defined in the table. 2. device storage elements are immune to seu affects. absolute maximum ratings note: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the opera tional sections is not recommend ed. exposure to absolute maxi mum rating conditio ns for extended periods may affect device reliability. recommended operating conditions parameter limit units total dose 1.0e6 rads(si) seu threshold 2 80 mev-cm 2 /mg sel threshold 120 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 symbol parameter limit units v dd supply voltage -0.3 to 7.0 v v i/o voltage any pin -.3 to v dd +.3 v t stg storage temperature range -65 to +150 c t j maximum junction temperature +175 c t ls lead temperature (soldering 5 seconds) +300 c jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd supply voltage 4.5 to 5.5 v v in input voltage any pin 0 to v dd v t c temperature range -55 to + 125 c
4 dc electrical characteristics 7 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. symbol parameter condition min max unit v il low-level input voltage 1 acts acs 0.8 .3v dd v v ih high-level input voltage 1 acts acs .5v dd .7v dd v i in input leakage current acts/acs v in = v dd or v ss -1 1 a v ol low-level output voltage 3 acts acs i ol = 8.0ma i ol = 100 a 0.40 0.25 v v oh high-level output voltage 3 acts acs i oh = -8.0ma i oh = -100 a .7v dd v dd - 0.25 v i oz three-state output leakage current v o = v dd and v ss -20 20 a i os short-circuit output current 2 ,4 acts/acs v o = v dd and v ss -200 200 ma i ol output current 10 (sink) v in = v dd or v ss v ol = 0.4v 8 ma i oh output current 10 (source) v in = v dd or v ss v oh = v dd - 0.4v -8 ma p total power dissipation 2, 8, 9 c l = 50pf 1.9 mw/ mhz i ddq quiescent supply current v dd = 5.5v 10 a i ddq quiescent supply current delta acts for input under test v in = v dd - 2.1v for all other inputs v in = v dd or v ss v dd = 5.5v 1.6 ma c in input capacitance 5 ? = 1mhz @ 0v 15 pf c out output capacitance 5 ? = 1mhz @ 0v 15 pf
5 notes: 1. functional tests are conducted in accordance with mil-std-883 with the followi ng input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any inpu t voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 2. supplied as a design limit bu t not guaranteed or tested. 3. per mil-prf-38535, for current density 5.0e5 amps/cm 2 , the maximum product of load capac itance (per output buff er) times frequency should not exceed 3,765 pf/mhz. 4. not more than one output may be shorted at a time for maximum duration of one second. 5. capacitance measured for initial qualifi cation and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 6. maximum allowable relative shift equals 50mv. 7. all specifications valid for radiation dose 1e6 rads(si). 8. power does not include power contribution of any ttl output sink current. 9. power dissipation specified per switching output. 10. this value is guaranteed based on characterization data, but not tested.
6 ac electrical characteristics 2 (v dd = 5.0v 10%; v ss = 0v 6 , -55 c < t c < +125 c); unless otherwise noted, tc is per the temperature range ordered. notes: 1. maximum allowable relative shift equals 50mv. 2. all specifications valid for radiation dose 1e6 rads(si). symbol parameter minimum maximum unit t plh data to qn 1 14 ns t phl data to qn 1 16 ns t plh c to qn 1 16 ns t phl c to qn 1 18 ns t pzl oc low to qn 1 14 ns t pzh oc low to qn 1 14 ns t plz oc high to qn three-state 1 14 ns t phz oc high to qn three-state 1 14 ns f max maximum clock frequency 71 mhz t su data setup time before c 5 ns t h data hold time after c 4 ns t w minimum pulse width c high 7 ns
7 packaging side-brazed packages
8 flatpack packages
9 UT54ACS373/ut54acts373: smd 5962 ***** ** * * * * lead finish: (notes 1 & 2) a = solder c = gold x = optional package type: x = 20-lead ceramic botto m-brazed dual-in-line flatpack c = 20-lead ceramic side-brazed dip class designator: q = qml class q v = qml class v device type: 01 drawing number : 96588 = UT54ACS373 96589 = ut54acts373 total dose: (notes 3 & 4) r = 1e5 rads(si) f = 3e5 rads(si) g = 5e5 rads(si) h = 1e6 rads(si) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, pa rt marking will match the lead finish and w ill be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. for protot ype inquiries, contact factory. 4. device type 02 is only offered with a tid tolerance guarantee of 3e5 rads(si) or 1e6 rads(si) and is tested in accordance wi th mil-std-883 test method 1019 condition a and section 3.11.2 . device type 03 is only offered with a tid tolerance guarantee of 1e5 rads(si), 3e5 rads(si) , and 5e5 rads(si), and is tested in accordance with mil-std-883 test method 1019 condition a.
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